Conventionally, the insulation-layer etching method and the plating pillar method are known as the interlayer connection forming techniques for thin-film multilayer wiring on an organic substrate consisting of materials such as ceramic. FIG. 4 shows the process of the insulation-layer etching method. This method forms a conductor 11 on a substrate 10 having a dielectric layer. Then, photoresist 12 is blanket-applied onto the conductor 11, which is selectively exposed and developed. The conductor 11 is selectively etched to form lower-layer wiring 13 on desired locations. Then, remaining photoresist is removed. A dielectric layer 14 consisting of photosensitive resin is deposited on the formed lower-layer wiring 13 to form via 15 by a dry or wet etching method and to expose the lower-layer wiring 13. Then, upper-layer wiring 16 is deposited on the via 15 and the lower-layer wiring 13 using a film forming technique such as electroless plating, deposition, and sputtering. Multilayer wiring is formed on the organic substrate through repeated formation of the dielectric and the wiring layers.
Published Unexamined Patent Application No. 51-118390 describes that a predetermined multilayer wiring structure is formed by forming a polyimide resin film on a printed circuit board on which Al wiring conductors are formed, then forming an organic Al-compound layer on the surface of the polyimide resin film, and removing parts of the organic Al-compound layer from the polyimide resin film and forming through-holes therein, and then forming a second conductor layer of Al in the through-holes.
Published Unexamined Japanese Patent Application No. 58-93298 describes that a lower-layer wiring pattern is formed through forming a wiring conductor layer on a substrate, and then forming a resist layer thereon; and that the resist layer is removed, forming through-holes, an interlayer dielectric film constituting multilayer wiring is formed by using polyimide-based resin, a resist film being formed on the dielectric layer, forming connecting through-holes, the dielectric layer being baked after removal of the resist film, upper-layer wiring being formed on the dielectric layer.
Published Unexamined Japanese Patent Application No. 60-180197 describes that multilayer wiring patterns are formed by forming a primary layer on a dielectric substrate, forming a photopolymer film on the wiring pattern, and exposing, photo-setting and developing the photopolymer film to form a photo-set film with via holes at predetermined positions. Then, secondary layer wiring patterns are formed on the photo-set film of the photopolymer used as an interlayer dielectric film and on the via hole portions, and said photopolymer-film forming processes and processes are repeated in turn thereafter.
Published Unexamined Japanese Patent Application No. 61-121393 and Published Unexamined Japanese Patent Application No. 61-127196, what is described is that using the above dielectric layer etching method, wiring patterns of materials such as copper, chromium is formed on a dielectric layer surface through plating, sputtering, or evapolation, and, at the same time, the via hole portions is made conductive in order to electrically connect with a lower-layer conductor pattern.
FIG. 5 shows the process of the plating pillar method process. In this method, lower-layer wiring 103 is deposited on a substrate 101 blanket-coated with polyimide resin using film forming techniques such as sputtering. A bonding layer such as chromium is placed between the lower-layer wiring 103 and the substrate 101. Moreover, photosensitive resist 104 is blanket-coarted on the lower-layer 103, which is removed after pattern exposure and development to form a resist hole 105. A plating pillar 106 is formed in the resist hole 105 through, for example, electroplating, and the resist 104 is removed by, for example, solvent. Then, the plating column is coated with polyimide 107 whose surface is smoothed by polishing to expose the head of the plating pillar 106, and to form upper-layer wiring 108 on it using a film forming technique such as sputtering. Multilayer wiring is formed by repeating the above processes.
Published Unexamined Japanese Patent Application No. 61-90496 describes a process in which a plating pillar is formed in a through-hole by forming a metal foil for conductor circuits on a dielectric substrate to form lower-layer wiring through photoresist application, pattern exposure, development, plating, resist removal, and etching. Then a polyimide film is formed and a through-hole is formed with a mechanical drill or laser beam at the portion to be made conductive, and next the plating pillar is formed through locally supplying plating solution and a laser beam.
Published Unexamined Japanese Patent Application No. 63-43396 describes a process in which multilayer wiring is formed by forming a lower layer on the entire surface of a multilayer wiring alumina substrate and press-fitting a positive-type dry film before obtaining resist patterns through exposure and development, forming a plating pillar in formed via holes through electroplating, and removing the plated resist pattern with solvent, before applying a dielectric layer, polishing the surface of the dielectric layer to expose the head of the plating column and coat it with a dielectric layer, forming via holes with a required diameter on the dielectric layer, sputtering copper inside the via holes and on the surface of the dielectric layer, and forming necessary circuit patterns through etching.
Published Unexamined Japanese Patent Application No. 63-244797 describes a process in which necessary wiring is formed by laminating a positive-type dry film on an alumina substrate with lower-layer wiring patterns formed on it to make resist patterns and forming resist holes for plating pillars through exposure and development and then plating the resist holes with copper sulfate to form a plating pillar, before removing said resist with acetone to coat the pillar with a polyimide dielectric layer, polishing the surface of the dielectric layer to expose the head of the plating pillar, and installing a copper layer on the surface of the dielectric layer and the head of the plating pillar.
Published Unexamined Japanese Patent Application No. 61-179598 describes a process in which wiring is formed by forming photoresist patterns on the surface of copper wiring patterns formed on a ceramic substrate as lower-layer wiring through ordinary photolithography technique, depositing a plating pillar through electroplating on the surface of the lower wiring layer exposed through the photoresist hole, applying polyimide resin to the entire exposed surface of the plating pillar and substrate, applying predetermined pressure to the lower-layer surface in the direction of the substrate to flat the surface, and evapolating an upper wiring layer at predetermined positions on the surface of the dielectric layer.
Published Unexamined Japanese Patent Application No. 62-263645 describes a process in which predetermined patterns are formed on a substrate by etching chromium and copper layers blanket-applied in turn on the substrate, blanket-applying the copper layer with positive photoresist, exposing and developing the resist to form an opening (via hole), sililating the positive photoresist, forming a plating pillar in the opening by dipping the opening in a molten-solder bath though the sililated resist remains as solder barrier, and connecting upper-layer wiring to the pillar.
Published Unexamined Japanese Patent Application No. 50-2059 describes that a dielectric substrate made of, for example, ceramic is covered with a copper layer as lower-layer wiring, photoresist is deposited on the copper layer, the photoresist is exposed and developed to form a resist hole, a conductive material (plating pillar) such as copper is deposited in the hole through electroplating, the esidual photoresist is removed when electroplating is completed, before a dielectric material such as epoxy resin is deposited, a copper layer is electroless-plated on the conductive and dielectric materials, and interlayer connection is performed.
According to the above-mentioned dielectric layer etching methods, however, the via diameter is limited to the minimum value allowing plating because the via formed by etching are required to be made conductive through plating. In addition, to electrically connect lower-layer wiring with upper-layer wiring, it is necessary to provide a land on the electric circuit at the bottom of the via. However, to accurately align the land with the via, the electric-circuit forming density cannot be increased because the via diameter must be increased (for example, about 0.1 mm).
Furthermore, when a via is formed in a dielectric layer through wet etching, the taper angle of the hole wall increases and refining becomes difficult because the dielectric layer is etched while old etching solution is being replaced with new solution. Moreover, disconnection may occur between the lower-layer wiring and the upper-layer wiring unless resist is completely removed from on the lower-layer wiring. Therefore, perfect etching is not always expected. When the inside of the via is coated, the device reliability is degraded unless a uniform plating layer is formed on the side wall and the bottom.
On the other hand, when a via is formed in a dielectric layer through dry etching, an organic substrate is not desirable because gas is produced, and a ceramic, silicone, or glass substrate is impracticable because etching takes a longer time unless the metal layer thickness is made thin.
The above-mentioned plating pillar method has the disadvantage that extra processes are needed because photoresist is applied to or removed from a dielectric layer only to form a via bump (plating pillar).